APU Noise

The NES APU noise channel generates pseudo-random 1-bit noise at 16 different frequencies.

   Timer --> Shift Register   Length Counter
                   |                |
                   v                v
Envelope -------> Gate ----------> Gate ---> (to mixer)

7  bit  0
---- ----
..LC VVVV
  || ||||
  || ++++- When C is set: channel volume value
  ||       When C is clear: envelope divider reload value
  |+------ Constant volume flag (override envelope with V)
  +------- Length counter halt flag and envelope loop flag

7  bit  0
---- ----
M... PPPP
|    ||||
|    ++++- Noise period
+--------- Periodic noise mode

The timer period is set to entry P of the following:

The period determines how many CPU cycles happen between shift register clocks. These periods are all even numbers because there are 2 CPU cycles in an APU cycle.

7  bit  0
---- ----
LLLL L...
|||| |
++++-+---- Length counter load value

Writing to this register also restarts envelope.

The shift register is 15 bits wide LFSR.

When the timer clocks the shift register, the following actions occur in order:

1. Feedback is calculated as the exclusive-OR of bit 0 and one other bit: bit 6 if periodic noise mode (M bit) is set, otherwise bit 1.
2. The shift register is shifted right by one bit.
3. Bit 14, the leftmost bit, is set to the feedback calculated earlier.

This results in a pseudo-random bit sequence, 32767 steps long when Mode flag is clear, and randomly 93 or 31 steps long otherwise. (The particular 31- or 93-step sequence depends on where in the 32767-step sequence the shift register was when Mode flag was set).

The mixer receives the current envelope volume except when

• bit 0 of the shift register is set, or
• the length counter is zero

Within the mixer, the DMC level has a noticeable effect on the noise’s audio level.

On power-up, the shift register is loaded with the value 1.

In the earliest revisions of the 2A03 CPU, the periodic noise flag (M bit) was nonexistent: the shift register always used bits 0 and 1 for feedback, and the lowest period (rate $F) lasts 2046 M2 cycles instead of 4068. These CPUs were used in the first batch of Famicom consoles (which were recalled), in Vs. System boards, and in the arcade games that used the 2A03 as a sound coprocessor. [1], [2]

The 93-step sequence is about a quarter tone (50 cents) sharp relative to A440 tuning. The approximate frequencies and pitches (in LilyPond’s variant of Helmholtz notation) are as follows:

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