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Example flow

LDA #$20 / STA $2006 Low-Level Hardware Flow

1. Instruction: LDA #$20

  • Opcode:* A9
  • Operand:* 20
  1. **CPU Fetch Opcode**
  2. CPU places **Program Counter (PC)** on address bus (A0–A15).
  3. NES address decoder asserts **CE (chip enable)** for **PRG ROM**.
  4. PRG ROM drives **data bus D0–D7** with opcode `A9`.
  5. CPU reads opcode into instruction register.
  1. **CPU Fetch Operand**
  2. CPU increments PC → address bus points to next byte.
  3. PRG ROM CE active, data bus outputs operand `20`.
  4. CPU reads operand → Accumulator (A) will later be loaded with `20`.
  1. **Execute LDA**
  2. CPU loads operand into **Accumulator (A)**.
  3. No external bus activity required for execution.

2. Instruction: STA $2006

  • Target:* PPUADDR (PPU register $2006)
  1. **CPU Places Address on Bus**
  2. CPU puts `$2006` on address bus (A0–A15).
  3. NES address decoder activates **PPU CE**, deactivates other devices.
  1. **CPU Drives Data Bus**
  2. CPU places **Accumulator value `20`** on data bus D0–D7.
  3. CPU asserts **WR (write)** signal.
  1. **PPU Latches Data**
  2. PPU detects **CE active + WR active**.
  3. `$2006` first write → high byte of VRAM address latched.
  4. `$2006` second write → low byte latched.
  5. PPU internal flip-flop tracks first/second write.

3. Bus & Signal Summary

StepCPU Address BusCPU Data BusCERD/WRNotes
Fetch Opcode (A9)PCD0–D7PRG ROM CE activeRDPRG ROM outputs opcode
Fetch Operand (20)PC+1D0–D7PRG ROM CE activeRDPRG ROM outputs operand
STA $2006$2006D0–D7 = AccumulatorPPU CE activeWRPPU latches VRAM address

4. Notes

  • Only one device drives the data bus at a time to prevent conflicts.
  • PPU registers $2000–$2007 are memory-mapped; accessed via address decoder.
  • Internal PPU latches track high/low byte for $2006 VRAM address writes.

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