INES Mapper 034

iNES Mapper 034 denotes the unrelated NINA-001/NINA-002 and BNROM circuit boards. The NES 2.0 Submapper differentiates the two:

• Submapper 1 denotes the NINA-001/NINA-002 circuit board used by Impossible Mission II,
• Submapper 2 denotes the I-IM/BNROM circuit board used by Mashou/Deadly Towers.

In the absence of valid submapper information, mapper 34 .NES files should be considered BNROM when the CHR-ROM size is 0-8 KiB, and NINA-001/NINA-002 when the CHR-ROM size is above 8 KiB.

The NINA-001 PCB supports 64 KiB of PRG-ROM capacity and uses a microcontroller to disable the CIC. The NINA-002 PCB integrates a CIC stunner inside the PRG-ROM.

• CPU $6000-$7FFF: 8 KiB of unbanked PRG-RAM.
• CPU $8000-$FFFF: 32 KiB window into 64 KiB of PRG-ROM
• PPU $0000-$0FFF: 4 KiB window into 64 KiB of CHR-ROM
• PPU $1000-$1FFF: 4 KiB window into 64 KiB of CHR-ROM
• Nametable arrangement: Fixed horizontal arrangement/vertical mirroring without solder pad on PCB. Emulators should honor the respective iNES header bit.

The registers overlapping PRG-RAM at the same addresses mean that reading the register’s address returns the last value written to the PRG-RAM, which is also the last value written to the register.

D~[.... ...A] A~[0111 1111 1111 1101]
           +- PRG A15 (32 KiB bank)

The power-on value is undefined; games should have a reset vector and handler in all PRG-ROM banks.

D~[.... DCBA] A~[0111 1111 1111 1110]
        ++++- CHR A15..A12 (4 KiB bank) at PPU $0000

D~[.... DCBA] A~[0111 1111 1111 1111]
        ++++- CHR A15..A12 (4 KiB bank) at PPU $1000

The NINA-001 board contains a 74LS133 (13-input NAND gate), 74LS74 (dual D flip-flop), 74HCT139 (dual 1-4 decoder), 74LS00 (quad 2-input NAND gate), two 74HCT173s (4-bit tristate D flip-flop), as well as a microcontroller labelled NINA to act as a CIC defeat mechanism. These 4 registers reside “on top” of PRG RAM: each write to the register goes both to the register and to the RAM location at the same address. Thus, reading the register’s address returns the last value written to the RAM, which is also the last value written to the register.

One 2-NAND and one half of the 74'139 together generate /RAMSEL. Another 2-NAND inverts that to form +RAMSEL. A third 2-NAND inverts R/W to produce +WR. The 13-NAND combines +RAMSEL, +WR, and A12…A2 to generate /REGSEL. The other half of the 74'139 uses /REGSEL, A1, and A0 to generate the latching signals for the three flip-flops.

The final 2-NAND inverts PPU A12. PPU A12 and PPU /A12 are fed to the two 74'173s /OE inputs, implementing a simple quad 1-of-2 multiplexer.

A NINA-002 board exists which integrated a CIC stunner inside the PRG ROM, which now has an unusual pinout. It is otherwise identical in function to the NINA-001 board.

This hardware has a trivial oversize definition that supports 8 MiB PRG and 1 MiB CHR, made by replacing the three flip-flops with 74'374s.

• CPU $8000-$FFFF: 32 KiB window into 128 KiB of PRG-ROM
• PPU $0000-$1FFF: 8 KiB of unbanked CHR-RAM/-ROM
• Nametable arrangement: Fixed; solder pad selects between Horizontal and Vertical

D~[.... ..BA] A~[1... .... .... ....]
          ++- PRG A16..A15 (32 KiB bank)

• The power-on value is undefined; games should have a reset vector and handler in all PRG-ROM banks.
• The original BNROM board is always subject to AND-type bus conflicts: the effective value is the value being written bitwise-AND’d with the PRG-ROM content at the address being written to.

• iNES Mapper 241 is a variation of BxROM with 8 KiB PRG-RAM at CPU $6000-$7FFF, avoids bus conflicts, and optionally supports an LPC speech chip.
• iNES Mapper 177 adds mapper-controlled nametable arrangement, in addition to having 8 KiB PRG-RAM and without bus conflicts.

Edit this page on GitHub