Taito X1-005

The Taito X1-005 is a ASIC mapper used in a few of their games. This mapper also contains 128 bytes of mapper-internal WRAM and can be battery backed-up. Board wriring variant for single screen nametable arrangement exists and is allocated at iNES Mapper 207.

• CPU $7F00-$7F7F: 128 B internal RAM
• CPU $7F80-$7FFF: Mirror of $7F00-$7F7F
• CPU $8000-$9FFF: 8 KiB switchable PRG-ROM bank
• CPU $A000-$BFFF: 8 KiB switchable PRG-ROM bank
• CPU $C000-$DFFF: 8 KiB switahable PRG-ROM bank
• CPU $E000-$FFFF: 8 KiB PRG-ROM bank, fixed to the last bank
• PPU $0000-$07FF: 2 KiB switchable CHR bank
• PPU $0800-$0FFF: 2 KiB switchable CHR bank
• PPU $1000-$13FF: 1 KiB switchable CHR bank
• PPU $1400-$17FF: 1 KiB switchable CHR bank
• PPU $1800-$1BFF: 1 KiB switchable CHR bank
• PPU $1C00-$1FFF: 1 KiB switchable CHR bank

The Taito X1-005 provides total 11 registers for PRG bankings, CHR bankings, mirroring setup and RAM enable. All registers exist at $7EFx and mirrored at $7E7x because the CPU A7 line is ignored. All registers are write-only.

7  bit  0
---- ----
CCCC CCCc
|||| ||||
++++-++++- Set CHR bank

Each 6 registers affect on:

• $7EF0: Switch bank at PPU $0000-$07FF
• $7EF1: Switch bank at PPU $0800-$0FFF
• $7EF2: Switch bank at PPU $1000-$13FF
• $7EF3: Switch bank at PPU $1400-$17FF
• $7EF4: Switch bank at PPU $1800-$1BFF
• $7EF5: Switch bank at PPU $1C00-$1FFF

Bit 0 of written bank number is ignored when switching 2K banks ($7EF0, $7EF1), just like other common mappers like MMC3, for example.

7  bit  0
---- ----
.... ...M
        |
        +- Nametable arrangement (0: vertical (A11); 1: horizontal (A10))

This register is not mirrored at $7EF7. This register only works in iNES Mapper 080. iNES Mapper 207 board handles mirroring differently and this register is ignored.

7  bit  0
---- ----
RRRR RRRR
|||| ||||
++++-++++- Enable read and write to internal RAM only when written value of this register is $A3

Writing $A3 here enables reading and writing to internal RAM, other values disable.

This register is mirrored at $7EF9. Writing to $7EF9 should make the same result as writing to $7EF8.

7  bit  0
---- ----
..PP PPPP
  || ||||
  ++-++++- Set PRG bank

Each 3 registers affect on:

• $7EFA: Switch bank at CPU $8000-$9FFF
• $7EFC: Switch bank at CPU $A000-$BFFF
• $7EFE: Switch bank at CPU $C000-$DFFF

In addition, they are mirrored at right next respective addresses, i.e, $7EFB is the mirror of $7EFA, $7EFD is $7EFC’s, so on.

• Unknown-purpose $7EF7 register
  • Currently unknown-purpose $7EF7 register doesn’t seem to doanything with the /RAMSEL of the chip. Did not affect any behaviors even when tested with $7EF8.
  • Reading from it returns open-bus.

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