VRC2 and VRC4

The Konami VRC2 and Konami VRC4 are two related ASIC mappers in the VRC^[1] family.

Because the VRC2 is mostly a subset of the VRC4, relevant games are often emulated as VRC4 only. iNES mappers 21, 22, 23 and 25 implement various board permutations, and NES 2.0 submappers may be used to disambiguate further.

Example games:

Variations VRC2a/b/c and VRC4a/b/c/d/e/f are referring to different PCB layouts. Considering the mapper chip itself, all VRC2 behave the same way and all VRC4 behave the same way. This section describes how each variation presents itself to the NES CPU considering the different PCBs.

The VRC2 and VRC4 were used with several similar but incompatible boards. The primary difference between them was having the mapper address lines connected in different ways. In particular, two lines chosen from A0-A7 will be used to select registers.

† The VRC2b PCBs include: 350603, 350636, 350926, 351179

* There’re no known official VRC4f boards being commercially produced, and this variant was only glanced at several pirate multicarts and single-game cartridges. As such, VRC4f should be considered as an unofficial variant.

The VRC2 has:

• CHR limit of 256 KiB
• 1 bit latch at $6000-$6FFF
• Only horizontal or vertical nametable layout.

The VRC4 has:

• CHR limit of 512 KiB
• Additional 8 KiB PRG bank at $C000
• Horizontal, vertical and 1-screen nametables.
• IRQ device

The VRC2a (mapper 22) additionally wires the CHR banking lines differently (see below).

Unlike VRC2’s, the RAM decoding circuit that’s part of the VRC4 itself only decodes RAM from $6000-$6FFF. For the one game with 8 KiB of RAM, an external circuit was added.

iNES mappers 21, 23 and 25 each implements two address mappings at the same time:

• 21: VRC4a, VRC4c
• 23: VRC2b + VRC4f, VRC4e
• 25: VRC2c + VRC4b, VRC4d

Because the address pairings do not overlap, and the games appear to use these registers in a well behaved manner, it is presumed sufficient for compatibility in most cases. Additionally, the VRC4 is always presumed for these three mappers.

With an NES 2.0 header, a submapper may be used to specify which address mapping to use, and either VRC2 or VRC4.

• PPU $0000-$03FF: 1 KiB switchable CHR bank
• PPU $0400-$07FF: 1 KiB switchable CHR bank
• PPU $0800-$0BFF: 1 KiB switchable CHR bank
• PPU $0C00-$0FFF: 1 KiB switchable CHR bank
• PPU $1000-$13FF: 1 KiB switchable CHR bank
• PPU $1400-$17FF: 1 KiB switchable CHR bank
• PPU $1800-$1BFF: 1 KiB switchable CHR bank
• PPU $1C00-$1FFF: 1 KiB switchable CHR bank

• CPU $6000-$6FFF: 1 bit latch, or
• CPU $6000-$7FFF: 8 KiB PRG RAM bank (optional)
• CPU $8000-$9FFF: 8 KiB switchable PRG ROM bank
• CPU $A000-$BFFF: 8 KiB switchable PRG ROM bank
• CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last 16 KiB

• CPU $6000-$6FFF: 2 KiB PRG RAM bank (mirrored once) (optional), or
• CPU $6000-$7FFF: 8 KiB PRG RAM bank (via extra circuit) (optional)
• CPU $8000-$9FFF (or $C000-$DFFF): 8 KiB switchable PRG ROM bank
• CPU $A000-$BFFF: 8 KiB switchable PRG ROM bank
• CPU $C000-$DFFF (or $8000-$9FFF): 8 KiB PRG ROM bank, fixed to the second-to-last bank
• CPU $E000-$FFFF: 8 KiB PRG ROM bank, fixed to the last bank

This page lists registers as they are in the VRC2b and VRC4f variants (iNES mapper 23).

7  bit  0
---------
.... ..MW
       |+- WRAM Control
       +-- Swap Mode

This register is VRC4 only.

When ‘W’ is clear:

• the 8 KiB page at $6000 is open bus, and WRAM content cannot be read nor written

When ‘W’ is set:

• the 8 KiB page at $6000 is WRAM, and WRAM content can be read and written

When ‘M’ is clear:

• the 8 KiB page at $8000 is controlled by the $800x register
• the 8 KiB page at $C000 is fixed to the second-to-last 8 KiB in the ROM

When ‘M’ is set:

• the 8 KiB page at $8000 is fixed to the second-to-last 8 KiB in the ROM
• the 8 KiB page at $C000 is controlled by the $800x register

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KiB PRG bank at $8000 or $C000 depending on Swap Mode

VRC2 does not have a Swap Mode and the bank this register will switch is always the $8000-$9FFF bank.

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KiB PRG bank at $A000

7  bit  0
---------
.... ..MM
       ||
       ++- Mirroring (0: vertical; 1: horizontal; 2: one-screen, lower bank; 3: one-screen, upper bank)

VRC2 supports only vertical or horizontal nametables. Bit 1 is ignored.

VRC4 only has this register at $9000 only. $9002 is used to select PRG swap mode instead (see above).

VRC2-using games are usually well-behaved and only write 0 or 1 to this register, but Konami Wai Wai World in one instance writes $FF instead^[2].

The VRC4 decodes writes to $9003 and emits an active low signal. No Konami games made use of this, but some unlicensed games, assigned to other mappers, added extra hardware behind this address.

  $B000        $B001
7  bit  0    7  bit  0
---------    ---------
.... LLLL    ...H HHHH
     ||||       | ||||
     ||||       +-++++- High 5 bits of 1 KiB CHR bank at PPU $0000
     ++++-------------- Low 4 bits

VRC2 only has 4 high bits of CHR select. $B001 bit 4 is ignored.

On VRC2a (mapper 22), the low bit is ignored (right shift value by 1).

  $B002        $B003
7  bit  0    7  bit  0
---------    ---------
.... LLLL    ...H HHHH
     ||||       | ||||
     ||||       +-++++- High 5 bits of 1 KiB CHR bank at PPU $0400
     ++++-------------- Low 4 bits

VRC2 only has 4 high bits of CHR select. $B003 bit 4 is ignored.

On VRC2a (mapper 22), the low bit is ignored (right shift value by 1).

The other six CHR bank selects continue the pattern:

$F000:  IRQ Latch, low 4 bits
$F001:  IRQ Latch, high 4 bits
$F002:  IRQ Control
$F003:  IRQ Acknowledge

Many VRC mappers use the same IRQ system. For details on IRQ operation, see VRC IRQs.

This only exists on VRC2.

How it was supposed to work:

7  bit  0
---------
.... .SCD
      |||
      ||+- Data to EEPROM (write) or from EEPROM (read)
      |+-- Clock to EEPROM (write only)
      +--- Chip Select (write only)

How it works in practice:

7  bit  0
---------
.... ...L
        |
        +- 1-bit latch value (r/w)

Reads from $6000-6FFF return open bus for the top 7 bits. Reads from $7000-7FFF only ever return open bus.

The VRC2 was supposed to have shipped with a Microwire interface for save games. However, Konami never used it, seemingly due to a defect in the VRC2.

Across all the VRC2-using boards, the Data from EEPROM pin has been connected to many different things. On 351618 (22) it’s connected to ground. On 350603, 350636, and 351179 it floats. On 350926 it’s connected to Data to EEPROM. On 351948 (25) it’s connected to ground but extra hardware keeps the VRC2 from seeing reads from $6000 so as to not conflict with PRG RAM.

Several games, including Contra (J) and Ganbare Goemon 2 (J), rely on the two Data pins being connected to each other, and so expect to be able to read the written value back. In these cases, the LSB agrees with the last value written and the upper seven bits are open bus, e.g. both LDA $6100 and LDA $6000 will return $60|latch. Returning neither open bus nor 0x00 will work, and these games will lock almost immediately after execution begins. Fortunately, no games ever rely on any other behavior.

Emulators that use the same VRC4 core (and its PRG RAM) for VRC2 emulation will have the effect simulated for them. However, only 351948 contains any RAM.

The VRC2 and VRC4 exist in a 40-pin PDIP package.

1. ↑ Forum thread: Several Famicom Nes Documents in Japanese indicate that VRC stands for “Virtual ROM Controller”
2. ↑ Forum thread: incorrect mirroring in Wai Wai World, and VRC2 testing.

• NES Mapper List by Disch
• Konami Mapper by goroh, translated by Sgt. Bowhack
• Comprehensive NES Mapper Document by \Firebug\ information about mapper’s initial state is inaccurate.
• The CHR registers really are 9 bits: http://forums.nesdev.org/viewtopic.php?t=8569

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